| CPC H03H 11/483 (2013.01) [H03H 11/481 (2013.01); H03H 11/488 (2013.01); H03H 11/52 (2013.01); H03H 11/53 (2013.01)] | 20 Claims |
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20. A system for configuring a second generation voltage-mode conveyor circuit (VCII) as a tunable impedance simulator and impedance multiplier, comprising:
one second generation voltage-mode conveyor circuit (VCII) including a positive input terminal Y, an impedance input terminal Z0, a negative input terminal, an impedance output terminal Z, and a signal output terminal X, wherein the impedance input terminal Z0 is configured to be selectable between a positive input impedance terminal and a negative input impedance terminal, where the VCII has a current gain β and a voltage gain α;
a first impedance Z1 connected to the positive input terminal Y, wherein an internal circuit of the first impedance Z1 comprises a resistor R1 in parallel with a capacitor C1;
a voltage source Vs connected to the first impedance Z1, the impedance input terminal Z0 and the negative input terminal wherein the voltage source V is configured to generate a voltage signal having an amplitude |Vs| at a frequency s;
a second impedance Z2 having a first contactor connected to the signal output terminal X and a second contactor connected to a ground, wherein an internal circuit of the second impedance Z2 comprises a resistor R2 in parallel with a capacitor C2;
a third impedance Z3 having a first contactor connected to the impedance output terminal Z, and a second contactor connected to the ground, wherein an internal circuit of the third impedance Z3 consists of a resistor R3; and
the VCII is configured to be tunable by selecting values for R1, C1, R2, C2, and R3, such that:
when the impedance input terminal Z0 is configured to be a positive input impedance terminal, an input impedance Zin, to the VCII is given by
 any one of:
a tunable active inductor simulator is configured by setting Z1=R1, C1=0, R2=0, Z2=1/sC2, and Z3=R3 such that the input impedance is given by Zin=sC2R1R3=sL, where L represents an inductor given by L=C2R1R3, and wherein a value of the inductor is tuned by a selection of a value of C2, a value of R1 and a value of R3;
a tunable capacitance multiplier is configured by setting Z1=1/sC1, R1=0, Z2=R2, C2=0, and Z3=R3, such that the input impedance is given by
 where the capacitance C1 is multiplied by R2/R3, and an amount of multiplication of C1 is tuned by a selection of a value of R2 and a value of R3; and
a tunable resistance multiplier is configured by setting Z1=R1, C1=0, Z2=R2, C2=0, and Z3=R3, such that the input impedance is given by
 where R1 is multiplied by R3/R2, and an amount of multiplication of R1 is tuned by a selection of a value of R2 and a value of R3; and
when the impedance input terminal, Z0, is configured to be a negative input impedance terminal, an input impedance, Zin, to the VCII is given by
 any one of:
a tunable negative active inductor simulator is configured by setting Z1=R1, C1=0, R2=0, Z2=1/sC2, and Z3=R3 such that the input impedance is given by Zin=SC2R1R3=sL, where L represents an inductor given by L=C2R1R3, and wherein a value of the inductor is tuned by a selection of a value of C2, a value of R1 and a value of R3,
a tunable negative capacitance simulator is configured by setting Z1=1/sC1, R1=0, Z2=R2, C2=0, and Z3=R3, such that the input impedance is given by
 where the capacitance C1 is multiplied by R2/R3, and an amount of multiplication of C1 is tuned by a selection of a value of R2 and a value of R3, and
a tunable negative resistance simulator is configured by setting Z1=R1, C1=0, Z2=R2, C2=0, and Z3=R3, such that the input impedance is given by
 where R1 is multiplied by R3/R2, and an amount of multiplication of R1 is tuned by a selection of a value of R2 and a value of R3.
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