US 12,155,358 B2
Transimpedance amplifier
Hiroaki Katsurai, Musashino (JP); and Kimikazu Sano, Musashino (JP)
Assigned to Nippon Telegraph and Telephone Corporation, Tokyo (JP)
Appl. No. 17/604,672
Filed by Nippon Telegraph and Telephone Corporation, Tokyo (JP)
PCT Filed May 8, 2019, PCT No. PCT/JP2019/018458
§ 371(c)(1), (2) Date Oct. 18, 2021,
PCT Pub. No. WO2020/225893, PCT Pub. Date Nov. 12, 2020.
Prior Publication US 2022/0216841 A1, Jul. 7, 2022
Int. Cl. H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03G 3/30 (2006.01); H03K 19/21 (2006.01)
CPC H03F 3/45475 (2013.01) [H03F 1/0205 (2013.01); H03G 3/30 (2013.01); H03K 19/21 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A transimpedance amplifier configured to convert a current signal into a voltage signal, comprising:
a transimpedance stage;
a gain control circuit configured to compare an output of the transimpedance stage with a reference voltage and output a gain control voltage; and
a reset signal output circuit configured to output a reset signal having a pulse width at a timing of at least one of a rise or a fall of the gain control voltage,
wherein the reset signal output circuit further comprises a delay circuit configured to delay the gain control voltage to produce the reset signal, and sets the pulse width in proportion to a delay amount by the delay circuit.