| CPC H01L 29/7848 (2013.01) [H01L 29/0847 (2013.01); H01L 29/1033 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an active pattern on a substrate;
a source/drain pattern on the active pattern;
a channel pattern provided on the active pattern and connected to the source/drain pattern, the channel pattern comprising semiconductor patterns, which are stacked to be spaced apart from each other;
a gate electrode extending in a first direction and crossing the channel pattern; and
a gate insulating layer interposed between the gate electrode and the channel pattern,
wherein the source/drain pattern comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer,
wherein the first semiconductor layer comprises a center portion and an edge portion, which is adjacent to a side of the center portion in the first direction,
wherein the edge portion comprises a first outer side surface in contact with the gate insulating layer,
wherein the center portion comprises a second outer side surface in contact with the gate insulating layer, and
wherein the second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.
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