US 12,154,969 B2
Semiconductor device structure with metal gate stack
Jung-Hao Chang, Taichung (TW); Li-Te Lin, Hsinchu (TW); and Pinyen Lin, Rochester, NY (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 22, 2021, as Appl. No. 17/532,568.
Application 17/532,568 is a division of application No. 16/676,057, filed on Nov. 6, 2019, granted, now 11,183,580.
Claims priority of provisional application 62/854,519, filed on May 30, 2019.
Prior Publication US 2022/0085189 A1, Mar. 17, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a semiconductor substrate;
a metal gate stack over the semiconductor substrate, wherein the metal gate stack comprises a gate dielectric layer and a work function layer over the gate dielectric layer, the gate dielectric layer has a vertical sidewall protruding from a top surface of the work function layer;
a protection element over the metal gate stack, wherein the vertical sidewall of the gate dielectric layer is in direct contact with the protection element; and
a spacer structure over a sidewall of the metal gate stack, wherein a top of the spacer structure is higher than a top of the gate dielectric layer by a first height difference, the top of the gate dielectric layer is higher than a top of the work function layer by a second height difference, and a ratio of the first height difference to the second height difference is smaller than about 1/14.