US 12,154,927 B2
Semiconductor structure
Yen-Ting Chiang, Tainan (TW); Chun-Yuan Chen, Tainan (TW); Hsiao-Hui Tseng, Tainan (TW); Sheng-Chan Li, Tainan (TW); Yu-Jen Wang, Kaohsiung (TW); Wei Chuang Wu, Tainan (TW); Shyh-Fann Ting, Tainan (TW); Jen-Cheng Liu, Hsin-Chu (TW); and Dun-Nian Yaung, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 18, 2022, as Appl. No. 17/866,603.
Application 17/069,665 is a division of application No. 15/937,210, filed on Mar. 27, 2018, granted, now 10,825,853, issued on Nov. 3, 2020.
Application 17/866,603 is a continuation of application No. 17/069,665, filed on Oct. 13, 2020, granted, now 11,430,823.
Claims priority of provisional application 62/583,906, filed on Nov. 9, 2017.
Prior Publication US 2022/0352218 A1, Nov. 3, 2022
Int. Cl. H01L 27/14 (2006.01); H01L 27/146 (2006.01)
CPC H01L 27/1463 (2013.01) [H01L 27/14687 (2013.01); H01L 27/14689 (2013.01); H01L 27/1464 (2013.01); H01L 27/14643 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor substrate including a first surface and a second surface opposite to the first surface;
an interconnection structure over the first surface of the semiconductor substrate;
a color filter disposed over the second surface of the semiconductor substrate; and
a first isolation structure in the semiconductor substrate, wherein the first isolation structure comprises:
a bottom portion;
an upper portion between the bottom portion and the interconnect structure; and
a dielectric diffusion barrier layer surrounding a sidewall of the upper portion,
wherein a top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure such that the top surface of the upper portion of the first isolation structure is between a top surface of the dielectric layer of the interconnection structure and the first surface of the semiconductor substrate.