US 12,154,917 B2
Semiconductor image sensor
Ikuo Kurachi, Tokyo (JP); Hiroshi Takano, Tokyo (JP); and Yasumasa Kashima, Tokyo (JP)
Assigned to Optohub Co., Ltd, Nagano (JP)
Appl. No. 17/603,572
Filed by Optohub Co., Ltd, Nagano (JP)
PCT Filed Apr. 10, 2020, PCT No. PCT/JP2020/016184
§ 371(c)(1), (2) Date Oct. 13, 2021,
PCT Pub. No. WO2021/205662, PCT Pub. Date Oct. 14, 2021.
Prior Publication US 2022/0199661 A1, Jun. 23, 2022
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14603 (2013.01) [H01L 27/1463 (2013.01); H01L 27/14649 (2013.01); H01L 27/14689 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor image sensor comprising:
a light receiving element formed in a silicon substrate under an insulation film of an SOI substrate comprising the silicon substrate having a main surface and a backside surface opposed to the main surface, the insulation film formed on the main surface of the silicon substrate and having a backside surface contacting with the main surface of the silicon substrate and a frontside surface opposed to the backside surface, and a semiconductor layer formed on the frontside surface of the insulation film, and composed of a pn junction diode formed in a vertical direction to the main surface of the silicon substrate and having sensitivity to near-infrared light; and
a high voltage generating circuit configured to generate an applied voltage for applying a reverse bias voltage to the pn junction diode,
a BOX capacitor having a first electrode as a portion of the semiconductor layer formed on the frontside surface of the insulation film and a second electrode as a first P+ diffusion layer formed in a P- well layer formed in the silicon substrate so as to be located near the main surface of the silicon substrate, the first P+ diffusion layer contacting with the backside surface of the insulation film,
wherein the first electrode is connected to an output of the high voltage generating circuit,
the pn junction diode contains a second P+ diffusion layer formed in the silicon substrate so as to be located near the main surface of the silicon substrate and an N+ diffusion layer formed on the backside surface of the silicon substrate,
an impurity concentration of a portion of the silicon substrate excluding the first P+ diffusion layer, the second P+ diffusion layer, and the P-well layer is in a range of 1×1012/cm3 to 1×1014/cm3, a film thickness of the silicon substrate is in a range of 300 μm to 700 μm, and the applied voltage is in a range of 10 V to 60 V.