US 12,154,913 B2
Display device
Daisuke Kubota, Atsugi (JP); and Ryo Hatsumi, Hadano (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 14, 2023, as Appl. No. 18/539,698.
Application 15/147,151 is a division of application No. 14/479,684, filed on Sep. 8, 2014, granted, now 9,337,214, issued on May 10, 2016.
Application 18/539,698 is a continuation of application No. 17/017,821, filed on Sep. 11, 2020, granted, now 11,848,331.
Application 17/017,821 is a continuation of application No. 16/532,974, filed on Aug. 6, 2019, granted, now 10,777,585, issued on Sep. 15, 2020.
Application 16/532,974 is a continuation of application No. 15/685,287, filed on Aug. 24, 2017, granted, now 10,559,602, issued on Feb. 11, 2020.
Application 15/685,287 is a continuation of application No. 15/147,151, filed on May 5, 2016, granted, now 9,748,279, issued on Aug. 29, 2017.
Claims priority of application No. 2013-190864 (JP), filed on Sep. 13, 2013; application No. 2013-249904 (JP), filed on Dec. 3, 2013; application No. 2014-047241 (JP), filed on Mar. 11, 2014; and application No. 2014-106477 (JP), filed on May 22, 2014.
Prior Publication US 2024/0186332 A1, Jun. 6, 2024
Int. Cl. H01L 27/12 (2006.01); G02F 1/1337 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/136 (2006.01); H01L 29/04 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/124 (2013.01) [G02F 1/133707 (2013.01); G02F 1/134309 (2013.01); G02F 1/134336 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); G02F 1/13606 (2021.01); H01L 27/1229 (2013.01); H01L 29/045 (2013.01); H01L 29/7869 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display device comprising:
a scan line having a region configured to be a gate electrode of a transistor;
a semiconductor film comprising a channel formation region of the transistor;
a first conductive film configured to be one of a source electrode and a drain electrode of the transistor;
a second conductive film having a first region configured to be the other of the source electrode and the drain electrode of the transistor and a second region configured to be a signal line;
a pixel electrode electrically connected to the first conductive film; and
a common electrode having a region overlapping with the pixel electrode with an insulating film provided therebetween,
wherein the first conductive film comprises a first region extending parallel to the signal line and a second region extending parallel to the scan line,
wherein the common electrode has a slit-shaped opening,
wherein the slit-shaped opening has a first bending point and a second bending point facing each other,
wherein in a plan view, the first bending point is located between the pixel electrode and the signal line,
wherein in the plan view, the pixel electrode has a region overlapping with the second region of the first conductive film, and
wherein a peripheral edge of the pixel electrode has a region extending along a direction parallel to a straight line connecting the first bending point and the second bending point.