| CPC H01L 27/124 (2013.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/78666 (2013.01); H01L 29/78675 (2013.01); H01L 29/7869 (2013.01); G02F 2202/10 (2013.01); G02F 2202/103 (2013.01); G02F 2202/104 (2013.01); G09G 3/3648 (2013.01); G09G 3/3688 (2013.01)] | 12 Claims |
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1. A display device comprising:
a first source line comprising a region extended in a first direction in a plan view;
a second source line comprising a region extending in the first direction and adjacent to the first source line in a second direction orthogonal to the first direction;
a first gate line and a second gate line each comprising a region extending in the second direction in the plan view;
a first wiring and a second wiring each comprising a region extending in the second direction in the plan view;
a first pixel comprising:
a first transistor electrically connected with the first source line and the first gate line; and
a first capacitor electrically connected with the first wiring; and
a second pixel adjacent to the first pixel in a column direction, the second pixel comprising:
a second transistor and electrically connected with the second source line and the second gate line; and
a second capacitor electrically connected with the second wiring,
wherein a semiconductor layer of the first transistor is electrically connected to the first source line through a first conductive layer,
wherein in the plan view, the first wiring comprises a partially widening region,
wherein the partially widening region comprises a part overlapping with a second conductive layer provided in a same layer as the first source line and the second source line,
wherein the first conductive layer is provided in a layer different from the second conductive layer, the first source line, and the second source line, and
wherein each of the semiconductor layer of the first transistor and a semiconductor layer of the second transistor comprises silicon.
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5. A display device comprising:
a first source line comprising a region extended in a first direction in a plan view;
a second source line comprising a region extending in the first direction and adjacent to the first source line in a second direction orthogonal to the first direction;
a first gate line and a second gate line each comprising a region extending in the second direction in the plan view;
a first wiring and a second wiring each comprising a region extending in the second direction in the plan view;
a first pixel comprising:
a first transistor electrically connected with the first source line and the first gate line; and
a first capacitor electrically connected with the first wiring; and
a second pixel adjacent to the first pixel in a column direction, the second pixel comprising:
a second transistor and electrically connected with the second source line and the second gate line; and
a second capacitor electrically connected with the second wiring,
wherein a semiconductor layer of the first transistor is electrically connected to the first source line through a first conductive layer,
wherein in the plan view, the second wiring is provided between the first gate line and the second gate line,
wherein in the plan view, the first wiring comprises a partially widening region,
wherein the partially widening region comprises a part overlapping with a second conductive layer provided in a same layer as the first source line and the second source line,
wherein the first conductive layer is provided in a layer different from the second conductive layer, the first source line, and the second source line, and
wherein each of the semiconductor layer of the first transistor and a semiconductor layer of the second transistor comprises silicon.
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9. A display device comprising:
a first source line comprising a region extended in a first direction in a plan view;
a second source line comprising a region extending in the first direction and adjacent to the first source line in a second direction orthogonal to the first direction;
a first gate line and a second gate line each comprising a region extending in the second direction in the plan view;
a first wiring and a second wiring each comprising a region extending in the second direction in the plan view;
a first pixel comprising:
a first transistor electrically connected with the first source line and the first gate line; and
a first capacitor electrically connected with the first wiring; and
a second pixel adjacent to the first pixel in a column direction, the second pixel comprising:
a second transistor and electrically connected with the second source line and the second gate line; and
a second capacitor electrically connected with the second wiring,
wherein a semiconductor layer of the first transistor is electrically connected to the first source line through a first conductive layer,
wherein in the plan view, the first gate line is provided between the first wiring and the second wiring,
wherein in the plan view, the first wiring comprises a partially widening region,
wherein the partially widening region comprises a part overlapping with a second conductive layer provided in a same layer as the first source line and the second source line,
wherein the first conductive layer is provided in a layer different from the second conductive layer, the first source line, and the second source line, and
wherein each of the semiconductor layer of the first transistor and a semiconductor layer of the second transistor comprises silicon.
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