US 12,154,878 B2
Semiconductor device
Christoph Kutter, Munich (DE); Ewald Soutschek, Neubiberg (DE); and Georg Meyer-Berg, Munich (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,658.
Application 17/552,550 is a division of application No. 16/866,109, filed on May 4, 2020, granted, now 11,233,027, issued on Jan. 25, 2022.
Application 14/669,219 is a division of application No. 13/152,971, filed on Jun. 3, 2011, abandoned.
Application 17/855,658 is a continuation of application No. 17/552,550, filed on Dec. 16, 2021, granted, now 11,848,294.
Application 16/866,109 is a continuation of application No. 16/221,000, filed on Dec. 14, 2018, granted, now 10,679,959, issued on Jun. 9, 2020.
Application 16/221,000 is a continuation of application No. 14/669,219, filed on Mar. 26, 2015, granted, now 10,529,678, issued on Jan. 7, 2020.
Application 13/152,971 is a continuation of application No. 11/965,081, filed on Dec. 27, 2007, abandoned.
Prior Publication US 2022/0336399 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/12 (2006.01); H01L 23/48 (2006.01); H01L 23/50 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 21/6835 (2013.01); H01L 23/12 (2013.01); H01L 23/48 (2013.01); H01L 23/50 (2013.01); H01L 23/5381 (2013.01); H01L 23/5389 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 21/568 (2013.01); H01L 2224/02 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/20 (2013.01); H01L 2224/92 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15312 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19015 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19104 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor chip having a face comprising a first contact element and a second contact element, the semiconductor chip having a backside opposite the face, and the semiconductor chip having a first sidewall and a second sidewall, the second sidewall opposite the first sidewall;
a mold mass in contact with the first sidewall and the second sidewall of the semiconductor chip, the mold mass having a top surface co-planar with the face of the semiconductor chip;
a first dielectric layer having a first side opposite a second side, the first side of the first dielectric layer on the face of the chip and on the mold mass;
a first contact and a second contact within the first dielectric layer, the first contact coupled to the first contact element of the semiconductor chip, and the second contact coupled to the second contact element of the semiconductor chip;
a metallization layer on the second side of the first dielectric layer, the metallization layer comprising a first conducting element, a second conducting element and a third conducting element, the first conducting element coupled to the first contact, the second conducting element coupled to the second contact, and the third conducting element between the first conducting element and the second conducting element; and
a second dielectric layer on the metallization layer.