CPC H01L 23/66 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01Q 9/0407 (2013.01); H01Q 19/005 (2013.01); H01L 2221/68372 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/214 (2013.01)] | 20 Claims |
1. A method of manufacturing a semiconductor package, the method comprising:
forming a structure including a frame, a semiconductor chip, and a dielectric filling member, the frame including a conductive material and having a mounting space and a plurality of through holes, the semiconductor chip located in the mounting space, and the dielectric filling member filling the mounting space and the plurality of through holes and covering a top surface of the frame;
forming a supporting wiring structure under the structure, the supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure, the first redistribution conductive structure being electrically connected to the semiconductor chip;
forming a plurality of connection structures through the dielectric filling member, the plurality of connection structures extending in the plurality of through holes, electrically connecting the first redistribution conductive structure, and including a material having a higher electrical conductivity than the conductive material of the frame;
forming a cover wiring structure on the structure, the cover wiring structure including a second redistribution dielectric layer and a second redistribution conductive structure; and
attaching an antenna structure including a base board layer and an antenna conductive structure to the cover wiring structure.
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