CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 21/6835 (2013.01); H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3511 (2013.01)] | 2 Claims |
1. A method for fabricating a flip-chip packaging substrate, comprising:
providing an insulating portion having opposite first and second sides;
forming a plurality of first openings from on the first side of the insulating portion toward the second side of the insulating portion;
forming from on the second side of the insulating portion toward the first side of the insulating portion a plurality of second openings corresponding in position to the first openings, wherein corresponding ones of the first and second openings communicate with each other;
forming first conductive posts in the first openings, and forming second conductive posts in the second openings, in a manner that the first conductive posts and the second conductive posts are stacked on and in contact with one another, wherein the second conductive posts and the first conductive posts serve as conductive portions, and the insulating portion and the conductive portions serve as a core layer structure having opposite first and second surfaces, wherein end surfaces of the first conductive posts and the second conductive posts have different sizes; and
forming a circuit portion of a build-up type on the first and second surfaces of the core layer structure at the same or different times with the circuit portion electrically connected to the conductive portions,
wherein two ends of the first conductive posts are free from being formed with pad structures,
wherein two ends of the second conductive posts are free from being formed with pad structures,
wherein the circuit portion includes circuit structures formed on the first and second surfaces of the core layer structure,
wherein the circuit structures include a plurality of dielectric layers and a plurality of circuit layers bonded to the dielectric layers, and
wherein the circuit layers have vertical portions and horizontal portions, the vertical portions of the circuit layers are directly and electrically connected to the first conductive posts and the second conductive posts, and the dielectric layers are spaced between the horizontal portions of the circuit layers and the corresponding first and second surfaces of the core layer structure.
|