US 12,154,861 B2
Frame design in embedded die package
Woochan Kim, Sunnyvale, CA (US); Masamitsu Matasuura, Beppu (JP); Mutsumi Masumoto, Beppu (JP); Kengo Aoya, Beppu (JP); Hau Thanh Nguyen, San Jose, CA (US); Vivek Kishorechand Arora, San Jose, CA (US); Anindya Poddar, Sunnyvale, CA (US); and Hideaki Matsunaga, Beppu (JP)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 31, 2019, as Appl. No. 16/669,666.
Prior Publication US 2021/0134729 A1, May 6, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1033 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An embedded die package, comprising:
a layer having an exposed boundary on a surface of the embedded die package, wherein at least a portion of the exposed boundary comprises organic material;
at least one integrated circuit die positioned in the layer and within the exposed boundary; and
a dielectric material positioned in the layer and between the at least one integrated circuit die and a conductive member adjacent the at least one integrated circuit die, wherein a thickness of the conductive member is same as that of the integrated circuit die.