US 12,154,827 B2
Semiconductor device having plurality of insulators
Shunpei Yamazaki, Tokyo (JP); Toshihiko Takeuchi, Kanagawa (JP); Tsutomu Murakawa, Kanagawa (JP); Hiroki Komagata, Kanagawa (JP); Daisuke Matsubayashi, Kanagawa (JP); Noritaka Ishihara, Kanagawa (JP); and Yusuke Nonaka, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Oct. 24, 2023, as Appl. No. 18/383,086.
Application 18/383,086 is a continuation of application No. 17/518,614, filed on Nov. 4, 2021, granted, now 11,804,407.
Application 17/518,614 is a continuation of application No. 16/643,195, granted, now 11,195,758, issued on Dec. 7, 2021, previously published as PCT/IB2018/056534, filed on Aug. 28, 2018.
Claims priority of application No. 2017-170022 (JP), filed on Sep. 5, 2017; application No. 2017-170023 (JP), filed on Sep. 5, 2017; and application No. 2017-238210 (JP), filed on Dec. 13, 2017.
Prior Publication US 2024/0055299 A1, Feb. 15, 2024
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/8234 (2013.01) [H01L 27/06 (2013.01); H01L 27/088 (2013.01); H01L 29/7869 (2013.01); H10B 12/00 (2023.02)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first insulator;
an oxide semiconductor layer over the first insulator;
a second insulator comprising an opening over the oxide semiconductor layer;
a gate insulating film over the oxide semiconductor layer;
a gate electrode over the gate insulating film;
wherein the oxide semiconductor layer comprises In, Ga, and Zn,
wherein the first insulator and the second insulator comprise silicon oxide,
wherein the gate insulating film and the gate electrode are in the opening,
wherein the second insulator is in contact with the first insulator, and
wherein a top surface of the second insulator and a top surface of the gate electrode are coplanar.