| CPC G11C 7/222 (2013.01) [G06F 13/18 (2013.01); G11C 7/1063 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/1093 (2013.01); G06F 1/08 (2013.01); G06F 13/1668 (2013.01); G06F 13/1689 (2013.01); G06F 13/4234 (2013.01); G06F 13/4243 (2013.01)] | 20 Claims |
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1. A memory system comprising:
a memory chip; and
a memory controller configured to:
in a write operation,
transfer at least a first command to the memory chip;
transfer a first timing signal synchronized with a first clock to the memory chip; and
transfer first data synchronized with the first timing signal to the memory chip, and,
in a read operation,
transfer at least a second command to the memory chip; and
transfer a second timing signal synchronized with at least a second clock to the memory chip, the second clock having a frequency different from a frequency of the first clock, wherein
the memory chip is configured to, in the read operation,
generate a third timing signal synchronized with the second clock based on the second timing signal; and
transfer second data synchronized with the third timing signal to the memory controller.
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