a decoder suitable for generating warming-up cycle information indicating different warming-up cycles by decoding warming-up cycle preliminary information for setting one of the warming-up cycles;

a first data output control circuit suitable for generating a first latch read enable signal and a first data output control timing signal based on a first read enable signal, an internal enable signal and the warming-up cycle information, and generating, in response to the first data output control timing signal, a first data output control signal using the first latch read enable signal, one or more pulses of which are masked according to the warming-up cycle information; and

a second data output control circuit suitable for generating a second latch read enable signal and a second data output control timing signal based on a second read enable signal, which is complementary to the first read enable signal, the internal enable signal and the warming-up cycle information, and generating, in response to the second data output control timing signal, a second data output control signal using the second latch read enable signal, one or more pulses of which are masked according to the warming-up cycle information.