US 12,154,649 B2
Semiconductor device
Masato Sugita, Kanagawa (JP); Naoki Kimura, Kanagawa (JP); and Daisuke Kimura, Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jul. 5, 2023, as Appl. No. 18/347,517.
Application 18/347,517 is a continuation of application No. 17/565,713, filed on Dec. 30, 2021, granted, now 11,735,230.
Application 17/565,713 is a continuation of application No. 17/077,560, filed on Oct. 22, 2020, granted, now 11,244,708, issued on Feb. 8, 2022.
Application 17/077,560 is a continuation of application No. 16/736,945, filed on Jan. 8, 2020, granted, now 10,847,190, issued on Nov. 24, 2020.
Application 16/736,945 is a continuation of application No. 16/423,665, filed on May 28, 2019, granted, now 10,566,033, issued on Feb. 18, 2020.
Application 16/423,665 is a continuation of application No. 16/044,912, filed on Jul. 25, 2018, granted, now 10,339,981, issued on Jul. 2, 2019.
Application 16/044,912 is a continuation of application No. 15/646,360, filed on Jul. 11, 2017, granted, now 10,056,119, issued on Aug. 21, 2018.
Application 15/646,360 is a continuation of application No. 15/236,037, filed on Aug. 12, 2016, granted, now 9,721,621, issued on Aug. 1, 2017.
Application 15/236,037 is a continuation of application No. 14/328,552, filed on Jul. 10, 2014, granted, now 9,449,654, issued on Sep. 20, 2016.
Application 14/328,552 is a continuation of application No. 13/954,254, filed on Jul. 30, 2013, granted, now 8,817,513, issued on Aug. 26, 2014.
Application 13/954,254 is a continuation of application No. 13/731,599, filed on Dec. 31, 2012, granted, now 8,611,126, issued on Dec. 17, 2013.
Application 13/731,599 is a continuation of application No. 13/052,425, filed on Mar. 21, 2011, granted, now 8,379,427, issued on Feb. 19, 2013.
Claims priority of application No. 2011-37344 (JP), filed on Feb. 23, 2011.
Prior Publication US 2023/0343371 A1, Oct. 26, 2023
Int. Cl. G11C 5/02 (2006.01); G06F 13/42 (2006.01); G06F 16/9535 (2019.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01)
CPC G11C 5/04 (2013.01) [G06F 13/4282 (2013.01); G06F 16/9535 (2019.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 14/0018 (2013.01); G11C 16/04 (2013.01); G06F 2213/0032 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a volatile semiconductor memory;
first to n-th nonvolatile semiconductor memories (n is an integer equal to or larger than two), each including a plurality of ball-shaped electrodes on a bottom surface;
a controller configured to control the volatile semiconductor memory and the first to n-th nonvolatile semiconductor memories;
first to n-th circuit elements, each including a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a coat covering the film; and
a connector for connecting to an external device;
a multilayer wiring substrate on which the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, the first to n-th circuit elements, the controller, and the connector are mounted, the multilayer wiring substrate being shaped as a rectangle in a plan view, the connector being provided on a short side of the rectangle, wherein
the first to n-th nonvolatile semiconductor memories are aligned on a line in a longitudinal direction of the multilayer wiring substrate,
the controller is provided, in a plan view, between the connector and the first to n-th nonvolatile semiconductor memories,
the multilayer wiring substrate includes
a front surface layer with a wiring pattern formed thereon, the front surface layer being a layer on which the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, and the controller are mounted;
a rear surface layer with a wiring pattern formed thereon, the rear surface layer being a layer on which (n+1)-th to 2n-th nonvolatile semiconductor memories each including a plurality of ball-shaped electrodes on a bottom surface are mounted such that the (n+1)-th to 2n-th nonvolatile semiconductor memories are symmetric to the first to n-th nonvolatile semiconductor memories with respect to the multilayer wiring substrate,
a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers having a wiring pattern formed thereon,
first to n-th signal lines that connect the controller to the first to n-th circuit elements, respectively;
(n+1)-th to 2n-th signal lines that connect the first to n-th circuit elements to the first to n-th nonvolatile semiconductor memories, respectively, the (n+1)-th to 2n-th signal lines having a part that passes through the internal wiring layers; and
(2n+1)-th to 3n-th signal lines that branch from the (n+1)-th to 2n-th signal lines and connect the (n+1)-th to 2n-th nonvolatile semiconductor memories, respectively.