a memory array configured to provide read data to a first data bus;

N latch circuits coupled in parallel, wherein each latch circuit of the N latch circuits has data inputs coupled to the first data bus and is configured to store read data from the first data bus, and a latch input, wherein N is a positive integer greater than or equal to 2;

a data multiplexer having a data output, N data inputs respectively coupled to data outputs of the N latch circuits, and a selection input, wherein the data multiplexer is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on the selection input of the data multiplexer;

a logic circuit having a data input and a data output;

a data path coupled between the data output of the data multiplexer and the data input of the logic circuit, the data path configured to cause a propagation of data from the data output of the data multiplexer to the data input of the logic circuit;

a read control circuit configured to, in response to a read command, assert a first read signal to cause the memory array to provide the read data to the first data bus, and after asserting the first read signal, assert a first latch signal; and

a latch control circuit configured to provide a selection signal to the selection input of the data multiplexer, receive the first latch signal from the read control circuit, and provide a respective latching signal of a plurality of latching signals to the latch input of each latch circuit of the N latch circuits, wherein the latch control circuit is configured to assert the respective latching signal of the plurality of latching signals in response to the assertion of the first latch signal.