a plurality of first cell layers, each of which includes a plurality of first cells arrayed in a first plane and used as memory cells;

at least one second cell layer stacked on the first cell layer, and including a plurality of second cells arrayed in a second plane, the second cells not being used as memory cells;

a plurality of first wires, each of which is connected to the first cells arrayed in a first direction in the first plane;

a plurality of second wires, each of which is connected to the second cells arrayed in the first direction in the second plane;

a plurality of third wires, each of which is connected to the first cells and the second cell arrayed in a second direction in which the first and second cell layers are stacked;

a plurality of fourth wires, each of which is connected to the third wires arrayed in a third direction intersecting the first and second directions; and

a control circuit, wherein

the control circuit applies a first voltage to a selected first wire of the first wires when reading data from a selected cell selected from the first cells, the selected first wire being connected to the selected cell, and transmits a read voltage according to the data to a selected fourth wire of the fourth wires, the selected fourth wire being connected to the selected cell,

the control circuit transmits a reference voltage used as a reference for detecting the read voltage to a non-selected fourth wire of the fourth wires, other than the selected fourth wire, and

the control circuit applies a second voltage to a selected second wire of the second wires, the selected second wire being provided with the second cell between the selected second wire and the non-selected fourth wire.