a memory cell array comprising memory cells;

bit lines connected to the memory cells, wherein when a first memory cell of the memory cells and a first bit line of the bit lines are selected, a read current is supplied to the first memory cell through the first bit line to perform a read operation;

a bit line selection circuit comprising a first main select transistor and a plurality of first sub-select transistors connected in parallel with each other,

wherein each gate of the plurality of first sub-transistors is configured to receive a separated gate control signal, and the plurality of first sub-select transistors are configured to be the first memory cell through the first bit line to transfer the read current from the first bit line to the first memory cell; and

a sense amplifier configured to compare a reference current having a predetermined current value with a memory current drawn by the first memory cell and output an output signal based on an input voltage,

wherein the sense amplifier comprises an active load, the active load comprising a MOS transistor having a source terminal connected to an operating power supply through a first PMOS transistor and gate and drain terminals connected to the first main select transistor through a first NMOS transistor and configured to reduce the input voltage at a sense node.