US 12,154,610 B2
Semiconductor device and semiconductor system
Genta Watanabe, Tokyo (JP); Ken Matsubara, Tokyo (JP); Tomoya Saito, Tokyo (JP); Akihiko Kanda, Tokyo (JP); Koichi Takeda, Tokyo (JP); and Takahiro Shimoi, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Jun. 23, 2022, as Appl. No. 17/847,967.
Claims priority of application No. 2021-120948 (JP), filed on Jul. 21, 2021.
Prior Publication US 2023/0025357 A1, Jan. 26, 2023
Int. Cl. G11C 11/08 (2006.01); G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1677 (2013.01); G11C 11/1697 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of memory cells;
a write circuit for supplying a write current to the memory cells;
a power supply circuit for supplying power to the write circuit, wherein the power supply circuit includes:
a charge pump circuit for boosting an external power supply; and
a selection circuit for switching between a voltage of the external power supply and a boosted voltage boosted by the charge pump circuit to supply the power to the write circuit; and
a control circuit i) executes data write processing using the voltage of the external power supply, ii) determines whether a number of errors that occurred during the data write processing executed using the voltage of the external power supply is equal to or less than a predetermined number, iii) continue executing the data write processing using the voltage of the external power supply when the number of errors is not equal to or less than the predetermined number, and iv) control the selection circuit to switch from the voltage of the external power supply to the boosted voltage and execute data write processing using the boosted voltage when the number of errors is equal to or less than the predetermined number.