	US 12,154,510 B2
	Display substrate including multiple cascaded shift register units, preparation method thereof, and display device
Teng Chen, Beijing (CN); Faming Jiang, Beijing (CN); Ri Chen, Beijing (CN); Xinxing Jia, Beijing (CN); Weixin Meng, Beijing (CN); and Jonguk Kwak, Beijing (CN)
Assigned to Chongqing BOE Display Technology Co.,Ltd., Chongqing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/609,407
Filed by Chongqing BOE Display Technology Co.,Ltd., Chongqing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jan. 26, 2021, PCT No. PCT/CN2021/073726 § 371(c)(1), (2) Date Nov. 8, 2021, PCT Pub. No. WO2022/160088, PCT Pub. Date Aug. 4, 2022.
Prior Publication US 2023/0317015 A1, Oct. 5, 2023
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H10K 59/12 (2023.01); H10K 59/131 (2023.01)

CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); H10K 59/1201 (2023.02); H10K 59/1315 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01)]

17 Claims

1. A display substrate, comprising a display region and a peripheral region on a periphery of the display region, wherein

a gate driving circuit is arranged in the peripheral region, and the gate driving circuit comprises multiple cascaded shift register units, the shift register unit comprises at least one transistor of a first semiconductor type, at least one transistor of a second semiconductor type, and at least one capacitor, and types of the transistor of the first semiconductor type and the transistor of the second semiconductor type are different;

in a direction perpendicular to the display substrate, the display substrate comprises an underlay substrate, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer which are arranged on the underlay substrate;

the first semiconductor layer at least comprises an active layer of the at least one transistor of the second semiconductor type of the shift register unit;

the first conductive layer at least comprises a control electrode of the at least one transistor of the second semiconductor type and a first electrode of the at least one capacitor of the shift register unit;

the second semiconductor layer at least comprises an active layer of the at least one transistor of the first semiconductor type of the shift register unit;

the second conductive layer at least comprises a control electrode of the at least one transistor of the first semiconductor type and a second electrode of the at least one capacitor of the shift register unit; and

the third conductive layer at least comprises first electrodes and second electrodes of the at least one transistor of the first semiconductor type and the at least one transistor of the second semiconductor type of the shift register unit;

wherein the first conductive layer further comprises a third output terminal of the shift register unit; and the second semiconductor layer is on a side of the third output terminal away from the first semiconductor layer;

wherein the transistor of the second semiconductor type comprises a first transistor and a second transistor, and the transistor of the first semiconductor type comprises a third transistor and a fourth transistor;

wherein the first conductive layer further comprises a first output terminal and a second output terminal of the shift register unit; and

a control electrode of the second transistor and the second output terminal form an integrated structure, a control electrode of the first transistor is between the control electrode of the second transistor and the second output terminal, and the third output terminal is on a side of the control electrode of the first transistor away from the second output terminal.