US 12,154,482 B2
Pixel circuit and display panel
Liang Sun, Hubei (CN); and Mian Zeng, Hubei (CN)
Assigned to Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Wuhan (CN)
Appl. No. 17/432,948
Filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Hubei (CN)
PCT Filed Jun. 7, 2021, PCT No. PCT/CN2021/098536
§ 371(c)(1), (2) Date Aug. 23, 2021,
PCT Pub. No. WO2022/227231, PCT Pub. Date Nov. 3, 2022.
Claims priority of application No. 202110461626.2 (CN), filed on Apr. 27, 2021.
Prior Publication US 2024/0127738 A1, Apr. 18, 2024
Int. Cl. G09G 3/32 (2016.01); G09G 3/3233 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0262 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0626 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a first power line;
a second power line;
a light-emitting device and a drive transistor, connected in series between the first power line and the second power line;
a storage capacitor, electrically connected to a gate of the drive transistor;
a writing transistor, one of a source and a drain of the writing transistor electrically connected to the storage capacitor and the other one of the source and the drain of the writing transistor used to receive a data signal;
a transfer capacitor, electrically connected to the one of the source and the drain of the writing transistor;
a first switch transistor, one of the source and the drain of the first switch transistor electrically connected to the transfer capacitor and the one of the source and the drain of the writing transistor and the other one of the source and the drain of the first switch transistor electrically connected to one of the source and the drain of the drive transistor; and
a second switch transistor, wherein one of the source and the drain of the second switch transistor is electrically connected to the other one of the source and the drain of the drive transistor; the other one of the source and the drain of the second switch transistor is electrically connected to the storage capacitor and the gate of the drive transistor;
wherein the gate of the writing transistor is configured to receive a first control signal; the gate of the first switch transistor is configured to receive a second control signal; the gate of the second switch transistor is configured to receive the second control signal; in a same frame, a number of effective pulses of the first control signal is less than a number of effective pulses of the second control signal, and at least one effective pulse in the second control signal is as the same as an effective pulse of the first control signal.