| CPC G06F 9/467 (2013.01) [G06F 9/3016 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01)] | 14 Claims |
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1. A method for processing multiple transactions converted from a single transaction, the method being performed by a processor including at least one core and comprising:
determining, by a decoding circuit of the core, whether a size of a first transaction conforming to an instruction according to an instruction set architecture (ISA) is the same as a register size of the core;
in response to determining that the size of the first transaction is larger than the register size of the core, converting, by the decoding circuit or a load-store unit (LSU) of the core, the first transaction into a plurality of second transactions conforming to the register size of the core; and
transferring, by the LSU, the plurality of second transactions to a cache of the core,
wherein the LSU is configured to further transfer, to the cache, conversion information indicating whether the plurality of second transactions are converted from the first transaction.
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