US 12,153,926 B2
Processor-guided execution of offloaded instructions using fixed function operations
John Kalamatianos, Boxborough, MA (US); Michael T. Clark, Austin, TX (US); Marius Evers, Santa Clara, CA (US); William L. Walker, Fort Collins, CO (US); Paul Moyer, Fort Collins, CO (US); Jay Fleischman, Fort Collins, CO (US); and Jagadish B. Kotra, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Dec. 21, 2023, as Appl. No. 18/393,657.
Application 18/393,657 is a continuation of application No. 17/123,270, filed on Dec. 16, 2020, granted, now 11,868,777.
Prior Publication US 2024/0126552 A1, Apr. 18, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01)
CPC G06F 9/30181 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30098 (2013.01); G06F 9/30138 (2013.01); G06F 9/3834 (2013.01); G06F 9/3877 (2013.01); G06F 9/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
at least one processor core;
at least one memory controller configured for communication with a processing-in-memory (PIM) device of a memory device, wherein the processor is configured to:
write data identifying a set of operations to a command buffer of the PIM device; and
transmit one or more offload requests generated in response to one or more offload instructions, wherein the one or more offload requests direct the PIM device to execute the set of operations in the command buffer.