US 12,153,921 B2
Processor with macro-instruction achieving zero-latency data movement
Matthew Brandon Gately, Austin, TX (US); Eric Jonathan Deal, Austin, TX (US); Mark Willard Johnson, Austin, TX (US); and Daniel Thomas Riedler, Poway, TX (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Jun. 28, 2021, as Appl. No. 17/361,244.
Prior Publication US 2022/0413850 A1, Dec. 29, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3004 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30065 (2013.01); G06F 9/30105 (2013.01); G06F 9/3455 (2013.01); G06F 9/3853 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a hardware array processor to process array data in response to a macro-instruction,
wherein the hardware array processor processes the array data using loop operations, array iteration operations, and arithmetic logic unit (ALU) operations defined by the macro-instruction to achieve zero-latency data movement.