US 12,153,863 B2
Multi-processor simulation on a multi-core machine
James Kenney, Oxfordshire (GB); and Simon Davidmann, Oxfordshire (GB)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Feb. 3, 2023, as Appl. No. 18/105,554.
Application 18/105,554 is a continuation of application No. 15/030,216, granted, now 11,574,087, previously published as PCT/GB2014/053113, filed on Oct. 16, 2014.
Claims priority of application No. 1318473 (GB), filed on Oct. 18, 2013.
Prior Publication US 2023/0185991 A1, Jun. 15, 2023
Int. Cl. G06F 30/3308 (2020.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 30/20 (2020.01); G06F 30/33 (2020.01)
CPC G06F 30/3308 (2020.01) [G06F 9/4881 (2013.01); G06F 9/522 (2013.01); G06F 30/20 (2020.01); G06F 30/33 (2020.01)] 39 Claims
OG exemplary drawing
 
1. A method comprising:
running a plurality of simulated processors on a plurality of cores, in which simulation of the processors is performed in parallel on the plurality of cores and in which simulation of the processors is split into timeslices comprising instructions for the simulated processors; and
ensuring correct synchronization of the plurality of simulated processors within a first of the timeslices, including: running each processor on a core, and for each simulated processor:
suspending the instructions for the first timeslice for that simulated processor if a synch event is found within the instructions for the first timeslice for that simulated processor, or
running the simulated processor to the end of the first timeslice, if a synch event is not found within the instructions for the first timeslice for that simulated processor.