| CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/5678 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/0078 (2013.01); H10N 70/826 (2023.02); H10N 70/882 (2023.02)] | 21 Claims |
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1. A memory device including:
a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and
access circuitry to:
apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the plurality of program states;
apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the plurality of program states; and
during a read operation, apply a plurality of read voltages having positive polarities and a plurality of read voltages having negative polarities across the two terminals of the first memory cell to determine a program state of the first memory cell.
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