a variable-node circuit, configured to obtain a channel value read from a flash memory of the data storage device; and

a check-node circuit, configured to obtain a codeword difference from the variable-node circuit, and to calculate a syndrome according to the codeword difference,

wherein the variable-node circuit comprises a threshold-tracking circuit, configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status,

where in response to the threshold-tracking circuit determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status,

wherein the first flipping strategy is different from the post-processing flipping strategy,

wherein the trapping status comprises static trapping, and when the threshold-tracking circuit detects that the threshold used by the variable-node circuit has reached a predetermined number of LDPC iterative operations, the threshold-tracking circuit determines that the variable-node circuit has entered the static trapping, and sets a trapping-status signal to a high-logic state.