US 12,153,541 B2
Cache structure and utilization
Altug Koker, El Dorado Hills, CA (US); Lakshminarayanan Striramassarma, Folsom, CA (US); Aravindh Anantaraman, Folsom, CA (US); Valentin Andrei, San Jose, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Sean Coleman, Folsom, CA (US); Varghese George, Folsom, CA (US); Pattabhiraman K, Bangalore KA (IN); Mike MacPherson, Portland, OR (US); Subramaniam Maiyuran, Gold River, CA (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Vasanth Ranganathan, El Dorado Hills, CA (US); Joydeep Ray, Folsom, CA (US); Jayakrishna P S, Bangalore KA (IN); and Prasoonkumar Surti, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 17, 2022, as Appl. No. 17/674,703.
Application 17/674,703 is a continuation of application No. 17/429,291, previously published as PCT/US2020/022849, filed on Mar. 14, 2020.
Claims priority of provisional application 62/819,337, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,435, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,361, filed on Mar. 15, 2019.
Prior Publication US 2022/0171710 A1, Jun. 2, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 7/544 (2006.01); G06F 7/575 (2006.01); G06F 7/58 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/0866 (2016.01); G06F 12/0871 (2016.01); G06F 12/0875 (2016.01); G06F 12/0882 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/0893 (2016.01); G06F 12/0895 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 12/128 (2016.01); G06F 15/78 (2006.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06F 17/18 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); H03M 7/46 (2006.01); G06N 3/08 (2023.01); G06T 15/06 (2011.01)
CPC G06F 15/7839 (2013.01) [G06F 7/5443 (2013.01); G06F 7/575 (2013.01); G06F 7/588 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30065 (2013.01); G06F 9/30079 (2013.01); G06F 9/3887 (2013.01); G06F 9/5011 (2013.01); G06F 9/5077 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0866 (2013.01); G06F 12/0871 (2013.01); G06F 12/0875 (2013.01); G06F 12/0882 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0893 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 12/128 (2013.01); G06F 15/8046 (2013.01); G06F 17/16 (2013.01); G06F 17/18 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); H03M 7/46 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3867 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/302 (2013.01); G06F 2212/401 (2013.01); G06F 2212/455 (2013.01); G06F 2212/60 (2013.01); G06N 3/08 (2013.01); G06T 15/06 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A graphics processing unit (GPU) comprising:+
a plurality of groups of cores, each group of cores including:
a plurality of graphics cores;
a plurality of tensor cores; and
a ray tracing core;
a plurality of combined level 1 (L1) cache and shared memory units, each corresponding to a different group of cores of the plurality of groups of cores;
a level 2 (L2) cache to be shared by the plurality of groups of cores;
a plurality of memory controllers to couple the GPU to a memory; and
circuitry to access the L2 cache in response to requests for data units from the plurality of groups of cores, wherein the GPU, in response to a request for a first data unit, is to:
read the first data unit from the L2 cache when the first data unit is stored in the L2 cache or else fetch the first data unit from the memory into the L2 cache; and
overfetch additional data from the memory into the L2 cache, wherein an amount of the additional data is one of a plurality of selectable amounts of additional data, wherein the amount is to be selected based on an access for the first data unit, and wherein the amount of the additional data is to be selected dynamically for an access for the first data unit.