US 12,153,525 B2
Method and apparatus for verifying integrity in memory-disaggregated environment
Tae-Hoon Kim, Daejeon (KR); Kwang-Won Koh, Daejeon (KR); Kang-Ho Kim, Daejeon (KR); Chang-Dae Kim, Daejeon (KR); and Sang-Ho Eom, Seoul (KR)
Assigned to ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon (KR); and SYSGEAR CO., LTD., Seoul (KR)
Filed by Electronics and Telecommunications Research Institute, Daejeon (KR); and SYSGEAR CO., LTD., Seoul (KR)
Filed on Mar. 24, 2023, as Appl. No. 18/126,229.
Claims priority of application No. 10-2022-0037299 (KR), filed on Mar. 25, 2022; and application No. 10-2023-0014978 (KR), filed on Feb. 3, 2023.
Prior Publication US 2023/0305964 A1, Sep. 28, 2023
Int. Cl. G06F 12/0862 (2016.01); G06F 12/0864 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 12/0864 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for verifying integrity in a memory-disaggregated environment, comprising:
receiving write data corresponding to multiple hash values, the write data read from a remote memory, the multiple hash values generated based on the write data, the memory-disaggregated environment including local memory and the remote memory;
selecting a hash value among the multiple hash values for integrity verification based on an access latency of the remote memory to control latency from occurring during the integrity verification; and
verifying integrity of the write data read from the remote memory based on the hash value.