US 12,153,524 B2
Apparatus, system, and method for throttling prefetchers to prevent training on irregular memory accesses
John Kalamatianos, Boxborough, MA (US); Marko Scrbak, Austin, TX (US); Gabriel H. Loh, Bellevue, WA (US); and Akhil Arunkumar, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/957,358.
Prior Publication US 2024/0111676 A1, Apr. 4, 2024
Int. Cl. G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 2212/6028 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device comprising:
at least one prefetcher; and
a processing device communicatively coupled to the prefetcher, wherein the processing device is configured to:
execute a sequence of executable code;
detect a computer-readable throttling instruction that is included in the executable code and indicates a start of a throttling region of the executable code; and
in response to the computer-readable throttling instruction, prevent the prefetcher from being trained on one or more memory instructions included in the throttling region.