US 12,153,298 B2
Display device and electronic device
Shunpei Yamazaki, Tokyo (JP); Yoshiharu Hirakata, Kanagawa (JP); Tetsuji Ishitani, Kanagawa (JP); Daisuke Kubota, Kanagawa (JP); Ryo Hatsumi, Kanagawa (JP); Masaru Nakano, Kanagawa (JP); and Takashi Hamada, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on Apr. 21, 2023, as Appl. No. 18/137,648.
Application 18/137,648 is a continuation of application No. 17/848,628, filed on Jun. 24, 2022, granted, now 11,635,648.
Application 17/848,628 is a continuation of application No. 17/123,392, filed on Dec. 16, 2020, granted, now 11,372,276, issued on Jun. 28, 2022.
Application 17/123,392 is a continuation of application No. 14/948,720, filed on Nov. 23, 2015, granted, now 10,871,669, issued on Dec. 22, 2020.
Claims priority of application No. 2014-238566 (JP), filed on Nov. 26, 2014; application No. 2014-243313 (JP), filed on Dec. 1, 2014; application No. 2015-044820 (JP), filed on Mar. 6, 2015; and application No. 2015-109045 (JP), filed on May 28, 2015.
Prior Publication US 2024/0004229 A1, Jan. 4, 2024
Int. Cl. G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/133345 (2013.01) [G02F 1/133514 (2013.01); G02F 1/136213 (2013.01)] 2 Claims
OG exemplary drawing
 
2. A display device comprising a display portion, a peripheral circuit portion outside the display portion, and a peripheral portion outside the peripheral circuit portion, the display device comprising:
a substrate;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
a first oxide semiconductor layer over the second insulating layer, the first oxide semiconductor layer comprising a channel formation region of a transistor;
a second oxide semiconductor layer provided on a same layer as the first oxide semiconductor layer, the second oxide semiconductor layer comprising a first region which is configured to be a first electrode of a capacitor;
a third insulating layer over the first oxide semiconductor layer;
a fourth insulating layer over the second oxide semiconductor layer and the first third insulating layer;
a transparent conductive layer over the fourth insulating layer, the transparent conductive layer comprising a second region which is configured to be a second electrode of the capacitor; and
a coloring layer which transmits light,
wherein the transparent conductive layer is electrically connected to one of a source and a drain of the transistor,
wherein the fourth insulating layer is provided in the display portion, the peripheral circuit portion, and the peripheral portion,
wherein the fourth insulating layer is in contact with the second insulating layer in the peripheral portion,
wherein the first region of the second oxide semiconductor layer has a higher hydrogen concentration than the channel formation region, and
wherein the coloring layer does not overlap the second oxide semiconductor layer.