US 12,152,913 B2
Front-end circuit and encoder
Shu Hirata, Kanagawa (JP); Tomohiro Tahara, Tokyo (JP); Akio Kawai, Kanagawa (JP); and Shun Mugikura, Kanagawa (JP)
Assigned to MITUTOYO CORPORATION, Kawasaki (JP)
Filed by Mitutoyo Corporation, Kanagawa (JP)
Filed on Mar. 18, 2022, as Appl. No. 17/698,406.
Claims priority of application No. 2021-050176 (JP), filed on Mar. 24, 2021.
Prior Publication US 2022/0307866 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G01D 5/20 (2006.01); H03F 3/45 (2006.01); H03K 17/51 (2006.01); H04B 1/04 (2006.01)
CPC G01D 5/20 (2013.01) [H03F 3/45475 (2013.01); H03K 17/51 (2013.01); H04B 1/04 (2013.01); H04B 2001/045 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A front-end circuit comprising:
a preamplifier configured to amplify signals input to first and second input terminals;
a first switching circuit configured to receive first and second input signals and to alternatively and respectively output the first and second input signals to the first and second input terminals;
a switched capacitor circuit configured to sample two signals amplified by the preamplifier;
an integration circuit comprising a fully differential operational amplifier outputting signals obtained by amplifying differential signals that are input between third and fourth input terminals and are the two signals sampled by the switched capacitor circuit as differential signals between second and first output terminals, and first and second integration capacitors;
a second switching circuit configured to be capable of switching a connection relationship between the switched capacitor circuit, and one end of the first integration capacitor and one end of the second integration capacitor; and
a third switching circuit configured to be capable of switching a connection relationship between the other end of the first integration capacitor and the other end of the second integration capacitor, and third and fourth output terminals, wherein
double correlation sampling in which a cycle including sampling by the switched capacitor circuit and signal integration by the integration circuit is performed twice is performed, and
each time the cycle changes, the first switching circuit respectively switches output destinations of the first and second input signals between the first and second input terminals, the second switching circuit respectively switches output destinations of the two signals sampled by the switched capacitor circuit between the first and second integration capacitors, and the third switching circuit respectively switches connection destinations of the first and second integration capacitors between the third and fourth output terminals.