	US 11,829,299 B2
	Technologies for execute only transactional memory
David M. Durham, Beaverton, OR (US); Michael LeMay, Hillsboro, OR (US); and Men Long, Beaverton, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 12, 2022, as Appl. No. 17/819,418.
Application 17/819,418 is a continuation of application No. 16/724,603, filed on Dec. 23, 2019, granted, now 11,416,414.
Application 16/724,603 is a continuation of application No. 14/974,972, filed on Dec. 18, 2015, granted, now 10,558,582, issued on Feb. 11, 2020.
Claims priority of provisional application 62/236,405, filed on Oct. 2, 2015.
Prior Publication US 2022/0382684 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/1027 (2016.01); G06F 12/14 (2006.01); G06F 9/30 (2018.01); G06F 12/1045 (2016.01); G06F 12/1081 (2016.01)

CPC G06F 12/1027 (2013.01) [G06F 9/3005 (2013.01); G06F 12/1408 (2013.01); G06F 12/1475 (2013.01); G06F 12/1045 (2013.01); G06F 12/1081 (2013.01); G06F 2212/402 (2013.01); G06F 2212/50 (2013.01); G06F 2212/65 (2013.01); G06F 2212/652 (2013.01); G06F 2212/657 (2013.01); Y02D 10/00 (2018.01)]

12 Claims

1. A computing device comprising:

processor circuitry coupled to a memory, the processor circuitry to execute a page mis handler in response to a page miss, wherein the processor circuitry includes an instruction translation lookaside buffer and a data translation lookaside buffer,

wherein the processor circuitry to execute the page miss handler to: (i) determine whether a first page size associated with an execute only transactional range matches a second page size associated with a first physical memory address by a page table of the computing device and (ii) generate a page size mismatch fault in response to a determination that the first page size associated with the execute only transactional range does not match the second page size associated with the physical memory address by the page table.