US 12,484,460 B2
Phase-change memory cell having a compact structure
Philippe Boivin, Venelles (FR); and Simon Jeannot, Grenoble (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed on Nov. 10, 2023, as Appl. No. 18/506,383.
Application 17/328,917 is a division of application No. 16/457,855, filed on Jun. 28, 2019, granted, now 11,031,550, issued on Jun. 8, 2021.
Application 16/457,855 is a division of application No. 15/654,405, filed on Jul. 19, 2017, abandoned.
Application 15/654,405 is a division of application No. 15/098,025, filed on Apr. 13, 2016, granted, now 9,735,353, issued on Aug. 15, 2017.
Application 18/506,383 is a continuation of application No. 17/328,917, filed on May 24, 2021, granted, now 11,957,067.
Claims priority of application No. 1555733 (FR), filed on Jun. 23, 2015.
Prior Publication US 2024/0081160 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 70/20 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/061 (2023.02); H10N 70/253 (2023.02); H10N 70/823 (2023.02); H10N 70/826 (2023.02); H10N 70/8265 (2023.02); H10N 70/8413 (2023.02); H10N 70/8828 (2023.02); G11C 13/0004 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a semiconductor substrate;
a first insulating layer covering a surface of the semiconductor substrate;
a semiconductor active layer covering the first insulating layer;
a control gate of a selection transistor, the control gate being on the active layer and having a lateral flank;
a second insulating layer covering the lateral flank of the control gate;
first and second conduction regions of the selection transistor, the first and second conduction regions being in the active layer;
a trench through the active layer, the trench being defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;
a variable-resistance element electrically coupled to first conduction terminal of the selection transistor and including:
a first layer of resistive material covering the first lateral flank of the active layer in the trench, and
a second layer of a variable-resistance material that is in contact with an upper portion of the first layer and extends longitudinally in a plane parallel to the surface of the substrate; and
a dielectric trench isolation formed under the second layer and in the trench and covering a lateral flank of the first layer.