US 12,484,454 B2
Magnetic random access memory structure
Hui-Lin Wang, Taipei (TW); Che-Wei Chang, Taichung (TW); Ching-Hua Hsu, Kaohsiung (TW); Chen-Yi Weng, New Taipei (TW); and Po-Kai Hsu, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Mar. 27, 2023, as Appl. No. 18/126,486.
Claims priority of application No. 202310222244.3 (CN), filed on Mar. 9, 2023.
Prior Publication US 2024/0306514 A1, Sep. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/10 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/10 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 61/00 (2023.02); H10N 50/80 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A magnetic random access memory structure, comprising:
a substrate;
a first dielectric layer disposed on the substrate;
a first conductive via and a second conductive via in proximity to the first conductive via embedded in the first dielectric layer;
a bottom electrode layer disposed on the first dielectric layer, wherein the bottom electrode layer electrically connects the first conductive via with the second conductive via;
a spin orbit coupling layer disposed on the bottom electrode layer;
a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer;
a top electrode layer disposed on the MTJ element;
a nitride protective layer surrounding the MTJ element and the top electrode layer, and the nitride protective layer masking the spin orbit coupling layer;
a nitride spacer layer surrounding the nitride protective layer; and
a second dielectric layer surrounding the nitride spacer layer.