US 12,484,430 B2
Display panel with electrode surrounding pixel electrode
Jinyang Zhao, Guangdong (CN); Lixuan Chen, Guangdong (CN); and Zhiqing Shi, Guangdong (CN)
Assigned to Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/600,112
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Aug. 30, 2021, PCT No. PCT/CN2021/115370
§ 371(c)(1), (2) Date Sep. 30, 2021,
PCT Pub. No. WO2023/019634, PCT Pub. Date Feb. 23, 2023.
Claims priority of application No. 202110947907.9 (CN), filed on Aug. 18, 2021.
Prior Publication US 2024/0057461 A1, Feb. 15, 2024
Int. Cl. H10K 71/13 (2023.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01); H10K 59/126 (2023.01); H10K 71/00 (2023.01); H10K 102/00 (2023.01)
CPC H10K 71/135 (2023.02) [H10K 59/124 (2023.02); H10K 59/131 (2023.02); H10K 59/80522 (2023.02); H10K 59/126 (2023.02); H10K 71/811 (2023.02); H10K 2102/341 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A display panel, comprising:
an array substrate,
a pixel electrode layer disposed on the array substrate and including a plurality of pixel electrodes;
an electric field electrode layer disposed on the array substrate, wherein the electric field electrode layer is insulated from the pixel electrode layer, and the electric field electrode layer includes at least one electric field electrode at least surrounding a part of the pixel electrode,
wherein different voltages are applied to the pixel electrode layer and the electric field electrode layer to form a voltage difference, so that an electric field is formed between the pixel electrode layer and the electric field electrode layer, the electric field has a horizontal component and a vertical component, the vertical component of the electric field provides charged groups in a material of a light-emitting functional layer with a force to deposit on the pixel electrode layer;
wherein the array substrate comprises a light shielding layer, a first capacitor plate, a buffer layer, a semiconductor layer, a second capacitor plate, and a gate insulating layer, a gate layer, an interlayer insulating layer, a drain wiring, a source wiring, an auxiliary cathode wiring, a passivation layer, and a planarization layer which are sequentially stacked on a side of the substrate; and the pixel electrode layer and the electric field electrode layer are disposed on the planarization layer.