US 12,484,378 B1
Display having semiconducting oxide gate driver circuitry with adjustable threshold voltage
Pei-En Chang, San Jose, CA (US); Rungrot Kitsomboonloha, San Jose, CA (US); Akira Matsudaira, Santa Clara, CA (US); Fan Zhou, San Jose, CA (US); Hao-Lin Chiu, Los Gatos, CA (US); Kyung Wook Kim, Saratoga, CA (US); Pengyu Sun, San Jose, CA (US); Shih Chang Chang, Cupertino, CA (US); and Szu-Hsien Lee, Los Gatos, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 15, 2022, as Appl. No. 17/841,354.
Claims priority of provisional application 63/227,890, filed on Jul. 30, 2021.
Int. Cl. H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/1213 (2023.02) [H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display comprising:
an array of pixels; and
a chain of gate driver circuits configured to provide gate output signals to the array of pixels, wherein each gate driver circuit in the chain of gate driver circuits comprises:
a first transistor having a drain terminal coupled to a positive power supply line, a source terminal coupled to a gate driver output port on which one of the gate output signals is generated, a top gate terminal, and a bottom gate terminal;
a second transistor having a drain terminal coupled to the gate driver output port, a source terminal coupled to a ground power supply line, a top gate terminal, and a bottom gate terminal configured to receive an adjustable voltage; and
a third transistor having a drain terminal coupled to the top gate terminal of the second transistor, a source terminal coupled to the ground power supply line, a top gate terminal, and a bottom gate terminal configured to receive the adjustable voltage.