US 12,484,360 B2
Mechanisms for fabricating micro-LEDs
Chen Chen, San Diego, CA (US); and Jie Song, San Diego, CA (US)
Assigned to Saphlux, Inc., San Diego, CA (US)
Filed by Saphlux, Inc., San Diego, CA (US)
Filed on Feb. 14, 2025, as Appl. No. 19/054,743.
Application 19/054,743 is a continuation of application No. PCT/US2024/054001, filed on Oct. 31, 2024.
Claims priority of provisional application 63/594,947, filed on Oct. 31, 2023.
Prior Publication US 2025/0194318 A1, Jun. 12, 2025
Int. Cl. H01L 33/00 (2010.01); H10H 20/01 (2025.01); H10H 29/01 (2025.01); H10H 20/825 (2025.01)
CPC H10H 29/012 (2025.01) [H10H 20/01335 (2025.01); H10H 20/825 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method, comprising:
bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, wherein the semiconductor wafer comprises a first substrate, an LED epilayer formed on the first substrate, and a stress release pattern that divides the LED epilayer into a plurality of portions, and wherein the CMOS wafer comprises a second substrate and a plurality of interconnects formed on the second substrate;
etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures;
fabricating a dielectric layer on the plurality of micro-LED structures; and
fabricating an electrode layer on the plurality of micro-LED structures, wherein fabricating the electrode layer comprises fabricating a layer of a conductive material on the dielectric layer and top surfaces of the plurality of micro-LED structures.