US 12,484,323 B2
Stacked image sensor device and method of forming same
Wen-Chih Chiou, Zhunan Township (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 24, 2023, as Appl. No. 18/174,095.
Application 18/174,095 is a continuation of application No. 16/890,019, filed on Jun. 2, 2020, granted, now 11,594,571.
Claims priority of provisional application 62/982,250, filed on Feb. 27, 2020.
Prior Publication US 2023/0197760 A1, Jun. 22, 2023
Int. Cl. H10F 39/18 (2025.01); H10B 20/00 (2023.01)
CPC H10F 39/1895 (2025.01) [H10B 20/65 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
bonding a logic wafer to an image sensor wafer, a front side of the logic wafer comprising a first conductive pad, a front side of the image sensor wafer comprising a second conductive pad, wherein the logic wafer comprises a plurality of first dies on a single continuous semiconductor substrate, wherein the logic wafer comprises through vias, wherein bonding the logic wafer to the image sensor wafer comprises direct bonding the first conductive pad to the second conductive pad;
after bonding the logic wafer to the image sensor wafer, forming a first redistribution structure on a backside of the logic wafer, the backside of the logic wafer facing away from the image sensor wafer, wherein the first redistribution structure comprises a plurality of conductive layers and a plurality of insulating layers, wherein the through vias of the logic wafer contact respective conductive features of the first redistribution structure, wherein the first redistribution structure is free of a semiconductor substrate, the first redistribution structure comprising a third conductive pad;
after forming the first redistribution structure, bonding a die stack to the first redistribution structure, a width of the die stack being less than a width of one of the first dies of the plurality of first dies of the logic wafer, the die stack comprising:
a logic die, a front side of the logic die comprising a fourth conductive pad and a first dielectric layer, wherein the fourth conductive pad is directly bonded to the third conductive pad of the first redistribution structure, wherein the first dielectric layer is directly bonded to a first insulating layer of the plurality of insulating layers, a backside of the logic die comprising a fifth conductive pad; and
a memory die bonded to the logic die, a front side of the memory die comprising a sixth conductive pad, the sixth conductive pad being directly bonded to the fifth conductive pad, the logic die being bonded to the memory die using direct dielectric-to-dielectric bonds; and
after bonding the die stack to the first redistribution structure, forming an encapsulant on the first redistribution structure and around the die stack, the die stack having a first height as measured from the first redistribution structure, the encapsulant having a second height as measured from the first redistribution structure, the first height of the die stack being less than the second height of the encapsulant, the first redistribution structure completely separating the encapsulant from the logic wafer.