| CPC H10D 84/856 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0179 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method, comprising:
forming a plurality of first fin structures on a first active region of a semiconductor substrate, the plurality of first fin structures each having alternating first and second semiconductor layers;
forming a plurality of second fin structures over a second active region of the semiconductor substrate, the plurality of second fin structures each having alternating third and fourth semiconductor layers;
removing the first and third semiconductor layers, such that the second and fourth semiconductor layers are suspended over the semiconductor substrate, wherein the second and fourth semiconductor layers each has a maximum dimension extending in a first direction from a top view; and
forming a plurality of first metal gate structures surrounding each of the suspended second semiconductor layers, and a plurality of second metal gate structures surrounding each of the suspended fourth semiconductor layers, wherein the first and second gate structures each has a maximum dimension extending in a second direction from the top view, the second direction is perpendicular to the first direction, wherein the plurality of first metal gate structures have a first gate pitch, the plurality of second metal gate structures have a second gate pitch, the first gate pitch is a center-to-center distance between two adjacent first metal gate structures in the first direction, the second gate pitch is a center-to-center distance between two adjacent second metal gate structures in the first direction, and the second gate pitch is a first integer times the first gate pitch, and the first integer is two or more, and
wherein from a cross-sectional view taken along the first direction, one of the second semiconductor layers has opposing ends that respectively extends beyond opposing longitudinal sides of a corresponding one of the first metal gate structures in the first direction to directly contact source/drain regions.
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