| CPC H10D 84/853 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/797 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method of forming an integrated circuit structure, comprising:
forming a first semiconductor layer of a first semiconductor material over a substrate;
forming a stack of first and second semiconductor films interdigitated over the first semiconductor layer, the first and second semiconductor films having different semiconductor materials, wherein each of the first and second semiconductor films are thinner than the first semiconductor layer;
forming an isolation feature over the substrate and surrounding the first semiconductor layer, the stack of first and second semiconductor films protrudes above the isolation feature and defines an active region;
forming a gate stack over the active regions and spanning between a first and a second source/drain (S/D) region;
forming an S/D trench in the first and the second S/D regions by etching the stack of first and second semiconductor films in the first and the second S/D regions;
replacing the first semiconductor layer in the first S/D region with a second semiconductor layer of a second semiconductor material, wherein the second semiconductor material is different from the first semiconductor material; and
forming S/D features over the second semiconductor layer in the first S/D region and over the first semiconductor layer in the second S/D region.
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