US 12,484,295 B2
Method (and related apparatus) for forming a semiconductor device with reduced spacing between nanostructure field-effect transistors
Zhi-Chang Lin, Zhubei (TW); Huan-Chieh Su, Tianzhong Township (TW); and Kuo-Cheng Chiang, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 28, 2024, as Appl. No. 18/758,128.
Application 17/729,390 is a division of application No. 16/929,592, filed on Jul. 15, 2020, granted, now 11,322,493, issued on May 3, 2022.
Application 18/758,128 is a continuation of application No. 18/328,117, filed on Jun. 2, 2023, granted, now 12,034,004.
Application 18/328,117 is a continuation of application No. 17/729,390, filed on Apr. 26, 2022, granted, now 11,705,452, issued on Jul. 18, 2023.
Claims priority of provisional application 62/927,881, filed on Oct. 30, 2019.
Prior Publication US 2024/0355818 A1, Oct. 24, 2024
Int. Cl. H10D 84/83 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first semiconductor fin projecting from a semiconductor substrate;
a first plurality of semiconductor channel structures that are stacked over one another and over the first semiconductor fin;
a first plurality of gate dielectric structures encapsulating the first plurality of semiconductor channel structures, respectively;
a second semiconductor fin projecting from the semiconductor substrate and spaced apart laterally from the first semiconductor fin;
a second plurality of semiconductor channel structures that are stacked over one another and over the second semiconductor fin;
a second plurality of gate dielectric structures encapsulating the second plurality of semiconductor channel structures, respectively;
a dielectric structure projecting over the semiconductor substrate and spaced laterally between the first semiconductor fin and the second semiconductor fin; and
a gate electrode structure having a first lower portion, a second lower portion, and an upper portion, the first lower portion disposed over the first semiconductor fin and encapsulating the first plurality of gate dielectric structures, the second lower portion disposed over the second semiconductor fin and encapsulating the second plurality of gate dielectric structures, and the upper portion disposed over the dielectric structure and connecting the first lower portion of the gate electrode structure to the second lower portion of the gate electrode structure.