US 12,484,294 B2
Vertical fin-based field effect transistor (FinFET) with neutralized fin tips
Subhash Srinivas Pidaparthi, Santa Clara, CA (US); Clifford Drowley, Santa Clara, CA (US); Shahin Sharifzadeh, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Andrew Walker, Santa Clara, CA (US); and Francis Chai, Santa Clara, CA (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Jan. 17, 2023, as Appl. No. 18/097,693.
Claims priority of provisional application 63/304,512, filed on Jan. 28, 2022.
Prior Publication US 2023/0246027 A1, Aug. 3, 2023
Int. Cl. H10D 84/83 (2025.01); C30B 29/40 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/85 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/834 (2025.01) [C30B 29/403 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/8503 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A vertical fin-based field effect transistor (FinFET) device comprising:
an array of FinFETs comprising a plurality of rows and columns of separated fins, each of the separated fins having a fin length and a fin width measured laterally with respect to the fin length and including:
a first fin tip disposed at a first end of each of the separated fins;
a second fin tip disposed at a second end of each of the separated fins opposing the first end;
a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity; and
a source contact electrically coupled to the central region, wherein the first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity;
a first gate region laterally adjacent the first fin tip; and
a second gate region laterally adjacent the second fin tip.