| CPC H10D 84/83 (2025.01) [H01L 21/31116 (2013.01); H10D 64/01 (2025.01); H10D 64/015 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first active region and a second active region, on a substrate of the semiconductor device, that extend in a first direction;
a fin cut isolation region located between the first active region and the second active region;
a source or drain region in the first active region and the second active region;
a contact electrically connected to the source or drain region;
a shallow trench isolation (STI) layer adjacent to the first active region and the second active region;
a first gate region and a second gate region that extends in a second direction approximately perpendicular to the first direction;
a gate cut isolation region between the first gate region and the second gate region; and
at least one of:
a first boron nitride layer between the contact and a spacer associated with the contact,
a second boron nitride layer between the fin cut isolation region and the first active region and between the fin cut isolation region and the second active region, or
a third boron nitride layer between the gate cut isolation region and the first gate region and between the gate cut region and the second gate region.
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