US 12,484,292 B2
Methods of reducing parasitic capacitance in semicondutor devices
Kai-Hsuan Lee, Hsinchu (TW); Feng-Cheng Yang, Hsinchu County (TW); Yen-Ming Chen, Hsin-Chu County (TW); and Sai-Hooi Yeong, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jun. 10, 2024, as Appl. No. 18/738,707.
Application 17/350,177 is a division of application No. 16/399,553, filed on Apr. 30, 2019, granted, now 11,043,425, issued on Jun. 22, 2021.
Application 18/738,707 is a continuation of application No. 17/350,177, filed on Jun. 17, 2021, granted, now 12,009,263.
Claims priority of provisional application 62/725,403, filed on Aug. 31, 2018.
Prior Publication US 2024/0332084 A1, Oct. 3, 2024
Int. Cl. H01L 21/8234 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/764 (2006.01); H01L 27/088 (2006.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/28518 (2013.01); H01L 21/31055 (2013.01); H01L 21/764 (2013.01); H10D 30/62 (2025.01); H10D 62/115 (2025.01); H10D 64/015 (2025.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/0147 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a workpiece including a metal gate structure (MG), a first gate spacer disposed along a sidewall of the MG, a second gate spacer disposed along a sidewall of the first gate spacer, and a source/drain (S/D) feature disposed adjacent to the second gate spacer;
forming a contact trench over the S/D feature;
removing the second gate spacer to form an air gap between the MG and the S/D feature;
depositing a first dielectric layer over the S/D feature and partially filling the air gap;
removing a first portion of the first dielectric layer to expose a central portion of a top surface of the S/D feature, wherein a side portion of the top surface of the S/D feature remains under the first dielectric layer;
forming an S/D contact in the contact trench;
removing at least a second portion of the first dielectric layer to extend the air gap; and
depositing a second dielectric layer over the air gap.