| CPC H10D 84/0158 (2025.01) [H10D 30/014 (2025.01); H10D 84/0128 (2025.01); H10D 84/0142 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
|
1. A method for forming a stacked transistor device comprising a lower nanosheet field-effect transistor structure and an upper fin field-effect transistor structure, the method comprising:
forming on a substrate a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer on the lower device sub-stack, on the middle insulating layer an upper device sub-stack comprising an upper channel layer, and on the upper device sub-stack a capping layer;
forming a process layer embedding the fin structure;
subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing an upper surface of the upper device sub-stack;
forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap between the spacer layers, the reduced-width gap exposing a central portion of said upper surface;
subsequent to forming the spacer layers, etching back the process layer to a level below the lower device sub-stack;
splitting the upper channel layer by etching back said upper surface via the reduced-width gap to form two upper channel fins on the middle insulating layer;
subsequent to forming the upper channel fins, removing the spacer layers; and thereafter:
forming a gate structure across a channel region of the fin structure, the gate structure comprising a lower gate structure portion surrounding the lower channel nanosheets and an upper gate structure portion surrounding the upper channel fins; and
forming source and drain regions for the lower channel nanosheets and the upper channel fins at either side of the channel region.
|