| CPC H10D 84/013 (2025.01) [H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 30/6735 (2025.01); H10D 84/017 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |

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1. A semiconductor device, comprising:
an isolation structure formed in a substrate adjacent an active region;
a first gate structure and a second gate structure disposed over the active region;
a dummy structure disposed over the isolation structure,
wherein the first gate structure, second gate structure, and dummy gate structure extend in a first direction and are arranged in a second direction crossing the first direction;
a first source/drain epitaxial layer disposed between the dummy structure and the first gate structure and a second source/drain epitaxial layer disposed between the first gate structure and the second gate structure; and
an etch stop layer disposed over sidewalls of the dummy structure, first gate structure, and second gate structure,
wherein the etch stop layer has a step therein in between the dummy structure and the first gate structure; and
the second source/drain epitaxial layer extends a greater distance into the substrate than the first source/drain epitaxial layer.
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