| CPC H10D 64/254 (2025.01) [H10D 30/0212 (2025.01); H10D 64/01 (2025.01); H10D 64/251 (2025.01); H10D 64/256 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/017 (2025.01); H01L 23/345 (2013.01); H10D 30/6713 (2025.01); H10D 84/811 (2025.01)] | 20 Claims |

|
11. A semiconductor device comprising:
a first arrangement including first and second silicide layers correspondingly electrically coupled to opposing first and second surfaces of a doped first portion of an active region; and
a second arrangement including a third silicide layer electrically coupled to a first or second surface of a doped second portion of the active region,
a resistance of the doped second portion being sufficiently different than a resistance of the doped first portion such that the doped first portion of the first arrangement is effective as a heater for the doped second portion of the second arrangement.
|