US 12,484,277 B2
Tuning threshold voltage in field-effect transistors
Hsueh Wen Tsau, Miaoli County (TW); Ziwei Fang, Hsinchu (TW); Huang-Lin Chao, Hsinchu (TW); and Kuo-Liang Sung, Miaoli County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 28, 2023, as Appl. No. 18/521,223.
Application 17/676,691 is a division of application No. 16/573,733, filed on Sep. 17, 2019, granted, now 11,257,923, issued on Feb. 22, 2022.
Application 18/521,223 is a continuation of application No. 17/676,691, filed on Feb. 21, 2022, granted, now 11,855,181.
Claims priority of provisional application 62/745,004, filed on Oct. 12, 2018.
Prior Publication US 2024/0105813 A1, Mar. 28, 2024
Int. Cl. H01L 23/28 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H10D 30/00 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01)
CPC H10D 64/017 (2025.01) [H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/56 (2013.01); H01L 23/28 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an interfacial layer disposed over a semiconductor channel region;
a metal oxide layer disposed over the interfacial layer, wherein the metal oxide layer and the interfacial layer form a dipole moment, and wherein the metal oxide layer includes a first metal;
a high-k gate dielectric layer disposed over the metal oxide layer;
a metal halide layer disposed over the high-k gate dielectric layer, wherein the metal halide layer includes a second metal different from the first metal; and
a metal gate electrode disposed over the high-k gate dielectric layer.
 
10. A semiconductor structure, comprising:
a stack of channel layers;
an interfacial layer wrapping around each of the channel layers;
a high-k gate dielectric layer disposed over the interfacial layer;
a first metal-containing layer disposed between and directly contacting the interfacial layer and the high-k gate dielectric layer, wherein the first metal-containing layer includes a first metal, and wherein a concentration of the first metal is graded within the first metal-containing layer; and
a metal gate electrode disposed over the high-k gate dielectric layer.
 
15. A semiconductor structure, comprising:
an interfacial layer disposed over a plurality of semiconductor layers;
a metal oxide layer disposed over the interfacial layer;
a high-k gate dielectric layer disposed over the metal oxide layer;
a metal-containing layer disposed over the high-k gate dielectric layer; and
a metal gate electrode disposed over the metal-containing layer,
wherein the metal oxide layer and the high-k gate dielectric layer each include a first metal, and
wherein a concentration of the first metal is graded within the high-k gate dielectric layer.